In current semiconductor processing, FinFET devices in the 14 nm technology node and beyond are limited by contact resistance. Increased surface area and a higher doping concentration in source/drain (S/D) regions are known improvements, but are not easily implemented. Larger critical dimensions (CDs) for trench silicide (TS) have been used to achieve more S/D contact area, but CDs cannot be further increased without provoking gate to TS shorts and shorting between neighboring silicide trenches.
Another known method to reduce contact resistance is implanting dopant into S/D regions after high temperature processing and using laser spike anneal (LSA) to activate higher doping quantities. This approach achieves good results, but there is no proven patterning scheme to divide p-channel field-effect transistors (PFETs) and n-channel field-effect transistors (NFETs) within shared trenches in static random access memory (SRAM).
Another known method is to provide narrow trenches which typically sacrifice titanium silicide (TiSi) surface area in return for isolation from neighboring trenches. Trench implant and trench epitaxy experiments have shown significant contact resistance, but there is no known patterning solution for complementary metal oxide semiconductors (CMOS).
A need therefore exists for methodology enabling effective improvement of contact resistance in both PFET and NFET devices without additional masking layers, and the resulting device.